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ICS409MLF

ICS409MLF首页预览图
型号: ICS409MLF
PDF文件:
  • ICS409MLF PDF文件
  • ICS409MLF PDF在线浏览
功能描述: PC PERIPHERAL CLOCK
PDF文件大小: 137.09 Kbytes
PDF页数: 共5页
制造商: ICST[Integrated Circuit Systems]
制造商LOGO: ICST[Integrated Circuit Systems] LOGO
制造商网址: http://www.icst.com
捡单宝ICS409MLF
PDF页面索引
120%
PC PERIPHERAL CLOCK
MDS 409 C 2 Revision 111005
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l www.icst.com
ICS409
Pin Assignment 40/80M Frequency Selection
Note: See below for operations of frequency selection
Pin Descriptions
External Components
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50 trace (a
commonly used trace impedance), place a 33 resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20.
Decoupling Capacitor
As with any high performance mixed-signal IC, the
ICS409 must be isolated from system power supply
noise to perform optimally.
A decoupling capacitor of 0.01µF must be connected
between VDD and the PCB ground plane.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
been the crystal and device. Crystal capacitors must be
connected from each of the pins X1 and X1 to ground.
The value (in pF) of these crystal caps should equal
(C
L
-6pF)*2. In this equation, C
L
= crystal load
capacitance in pF. Example: For a crystal with a 15 pF
1
2
3
OE/LAT
4
GND
40/80M
25M
25M
X2
VDD
8
7
6
5
X1
8 Pin (150 mil) SOIC
40/80M (pin 5) Output Freq
0 40M
1 80M
Pin
Number
Pin
Name
Pin
Type
Pin Description
1 OE/LAT Input Disables or latches 40/80 MHz output dependant on pin 5 level.
2 X1 Input Crystal connection. Connect to 14.31818 MHz parallel mode crystal.
3 X2 Input Crystal connection. Connect to 14.31818 MHz parallel mode crystal.
4 VDD Power Connect to voltage supply.
5 40/80M Input/
Output
40M or 80M selection pin and clock output (see below for operation).
Tri-state when OE/LAT is low.
6 GND Power Connect to ground.
7 25M Output 25 MHz clock output.
8 25M Output 25 MHz clock output.
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