Analog Integrated Circuit Device Data
Freescale Semiconductor 7
17533
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
Figure 4. t
PLH
, t
PHL
, and t
PZH
Timing Figure 5. Low-Voltage Detection Timing Diagr am
10%
IN1,
50%
OUTA,
OUTB
IN2,
90%
t
PLH
t
PHL
OE
t
V
DD
DET
0%
I
M
50%
t
V
DD
DET
V
DD
DETon
V
DD
DEToff
90%
(<1.0 µA)
V
DD
2.5 V
1.5 V
Table 5. Truth Table
INPUT OUTPUT
OE
IN1A
IN2A
IN1B
IN2B
OUT1A
OUT2A
OUT1B
OUT2B
L L L L L
L H L H L
L L H L H
L H H Z Z
H X X Z Z
H = High.
L = Low.
Z = High impedance.
X = Don’t care.
OE pin is pulled up to V
DD
with internal resistance.
