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XRT73R12_07

XRT73R12_07首页预览图
型号: XRT73R12_07
PDF文件:
  • XRT73R12_07 PDF文件
  • XRT73R12_07 PDF在线浏览
功能描述: TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
PDF文件大小: 510.22 Kbytes
PDF页数: 共89页
制造商: EXAR[Exar Corporation]
制造商LOGO: EXAR[Exar Corporation] LOGO
制造商网址: http://www.exar.com
捡单宝XRT73R12_07
PDF页面索引
120%
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
(510) 668-7000
FAX (510) 668-7017
www.exar.com
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
JUNE 2007 REV. 1.0.2
GENERAL DESCRIPTION
The XRT73R12 is a twelve channel fully integrated
Line Interface Unit (LIU) featuring EXAR’s R
3
Technology (Reconfigurable, Relayless Redundancy)
for E3/DS3/STS-1 applications. The LIU incorporates
12 independent Receivers and Transmitters in a
single 420 Lead TBGA package.
Each channel of the XRT73R12 can be
independently configured to operate in E3 (34.368
MHz), DS3 (44.736 MHz) or STS-1 (51.84 MHz).
Each transmitter can be turned off and tri-stated for
redundancy support or for conserving power.
The XRT73R12’s differential receiver provides high
noise interference margin and is able to receive data
over 1000 feet of cable or with up to 12 dB of cable
attenuation.
The XRT73R12 provides a Parallel Microprocessor
Interface for programming and control.
The XRT73R12 supports analog, remote and digital
loop-backs. The device also has a built-in Pseudo
Random Binary Sequence (PRBS) generator and
detector with the ability to insert and detect single bit
error for diagnostic purposes.
APPLICATIONS
E3/DS3 Access Equipment
DSLAMs
Digital Cross Connect Systems
CSU/DSU Equipment
Routers
Fiber Optic Terminals
F
IGURE
1. B
LOCK
D
IAGRAM
OF
THE
XRT 73R12
ORDERING INFORMATION
P
ART
N
UMBER
P
ACKAGE
O
PERATING
T
EMPERATURE
R
ANGE
XRT73R12IB 420 Lead TBGA
-40
°
C to +85
°
C
XRT73R12
Channel 11
Channel 0
Channel n...
Device
Monitor
MTIP_n
MRing_n
DMO_n
Timing
Control
Tx
Pulse
Shaping
HDB3/
B3ZS
Encoder
Tx
Control
MUX
Line
Driver
Remote
LoopBack
HDB3/
B3ZS
Decoder
MUX
AGC/
Equalizer
Peak Detector
LOS
Detector
Slicer
µProcessor Interface
Local
LoopBack
Clock & Data
Recovery
Clock
Synthesizer
RD
WR
Addr[7:0]
CS
INT
D[7:0]
TxON
TxClk_n
TxPOS_n
TxNEG_n
RxClk_n
RxPOS_n
RxNEG/LCV_n
RLOS_n
RLOL_n
RTIP_n
RRing_n
TTIP_n
TRing_n
CLKOUT_n
SFM_en
E3Clk
DS3Clk
STS-Clk/12M
ICT
Pmode
RDY
PCLK
RESET
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