1
®
FN8132.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X5328, X5329
(Replaces X25328, X25329)
CPU Supervisor with 32Kbit SPI EEPROM
FEATURES
•Low V
CC
detection and reset assertion
—Five standard reset threshold voltages
—Re-program low V
CC
reset threshold voltage
using special programming sequence
—Reset signal valid to V
CC
= 1V
• Long battery life with low powe r consumption
—<1µA max standby current
—<400µA max active curre nt during read
• 32Kbits of EEPROM
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2 or all of EEPROM array with
Block Lock
™
protection
—In circuit programmable ROM mode
• 2MHz SPI interface modes (0,0 & 1,1)
• Minimize EEPROM programming time
—32-byte pa ge writ e mo de
—Self-timed write cycle
—5ms write cycle time (typical)
• 2.7V to 5.5V and 4.5V to 5.5V power supply
operation
• Available packages
—14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP
• Pb-free plus anneal available (RoHS compliant)
DESCRIPTION
These devices combine three popular functions, Power-
on Reset Control, Supply Voltage Supervision, and Block
Lock Protect Serial EEPROM Memory in one package.
This combination lowers system cost, reduces board
space requirements, and increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET
/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The device’s low V
CC
detection circuitry protects the
user’s system from low voltage conditions by holding
RESET
/RESET active when V
CC
falls below a mini-
mum V
CC
trip point. RESET/RESET remains asserted
until V
CC
returns to proper operating level and stabi-
lizes. Five industry standard V
TRIP
thresholds are
available, however, Intersil’s unique circuits allow the
threshold to be reprogrammed to meet custom
requirements or to fine-tune the threshold in applica-
tions requiring higher precision.
BLOCK DIAGRAM
Data
Register
Command
Decode &
Control
Logic
SI
SO
SCK
CS
V
CC
Reset
Timebase
Power-on and
Generation
V
TRIP
+
-
RESET/RESET
Reset
Low Voltage
Status
Register
Protect Logic
8Kbits
8Kbits
16Kbits
EEPROM Array
WP
X5328 = RESET
X5329 = RESET
Data Sheet October 17, 2005
