7107MEASUREINGRATIOMETRICVALUESOF
QUAD LOAD CELL
7106 USED AS A DIGITAL CENTIGRADE
THERMOMETER
FIGURE 19. CIRCUIT FOR DEVELOPING UNDERRANGE AND
OVERRANGE SIGNAL FROM
FIGURE 20. CIRCUIT FOR DEVELOPING UNDERRANGE AND
OVERRANGE SIGNALS FROM
Typical Applications
(Continued)
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
C
REF
C
REF
COMMON
IN HI
IN LO
A-Z
BUFF
INT
V -
G2
C3
A3
G3
GND
100pF
TO PIN 1
0.1µF
100kΩ
0.47µF
TO DISPLAY
The resistor values within the bridge are determined by the desired
sensitivity.
V+
0.22µF
47kΩ
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
C
REF
C
REF
COMMON
IN HI
IN LO
A-Z
BUFF
INT
V -
G2
C3
A3
G3
BP
100pF
TO PIN 1
0.1µF
0.01µF
100kΩ
100kΩ 1MΩ
9V
47kΩ
0.22µF
0.47µF
TO BACKPLANE
TO DISPLAY
A silicon diode-connected transistor has a temperature coefficient of
about -2mV/
o
C. Calibration is achieved by placing the sensing
transistor in ice water and adjusting the zeroing potentiometer for a
000.0 reading. The sensor should then be placed in boiling water
and the scale-factor potentiometer adjusted for a 100.0 reading.
SCALE
FACTOR
ADJUST
100kΩ 220kΩ
22kΩ
SILICON NPN
MPS 3704 OR
SIMILAR
ZERO
ADJUST
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
V+
D1
C1
B1
A1
F1
G1
E1
D2
C2
B2
A2
F2
E2
D3
B3
F3
E3
AB4
POL
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
C
REF
C
REF
COMMON
IN HI
IN LO
A-Z
BUFF
INT
V-
G2
C3
A3
G3
BP
O /RANGE
U /RANGE
CD4023 OR
74C10
CD4077
TO LOGIC
V
CC
V+
TO
LOGIC
V-
GND
O /RANGE
U /RANGE
CD4023 OR
74C10
TO LOGIC
V
CC
+5V
V-
33kΩ
The LM339 is required to
ensure logic compatibility
with heavy display loading.
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
V+
D1
C1
B1
A1
F1
G1
E1
D2
C2
B2
A2
F2
E2
D3
B3
F3
E3
AB4
POL
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
C
REF
C
REF
COMMON
IN HI
IN LO
A-Z
BUFF
INT
V-
G2
C3
A3
G3
BP
12kΩ
+
-
+
-
+
-
+
-