May 11, 2006 S29WS-J_00_A6 S29WS128J/064J 87
Data Sheet
Notes:
1. Status reads in figure are shown as asynchronous.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is
complete, the toggle bits will stop toggling.
3. While in Asynchronous mode, RDY will be low while the device is in embedded erase or programming mode.
Figure 30. Toggle Bit Timings (During Embedded Algorithm)
Notes:
1. The timings are similar to synchronous read timings.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is
complete, the toggle bits will stop toggling.
3. RDY is active with data (A18 = 0 in the Configuration Register). When A18 = 1 in the Configuration Register, RDY is active
one clock cycle before data.
Figure 31. Synchronous Data Polling Timings/Toggle Bit Timings
WE#
CE#
OE#
t
OE
Addresses
AVD#
t
OEH
t
CE
t
CH
t
OEZ
t
CEZ
Status Data Status Data
t
ACC
VA VA
Data
CE#
CLK
AVD#
Addresses
OE#
Data
RDY
Status Data
Status Data
VA
VA
t
IACC
t
IACC