86 S29WS128J/064J S29WS-J_00_A6 May 11, 2006
Data Sheet
Note: Use setup and hold times from conventional program operation.
Figure 28. Accelerated Unlock Bypass Programming Timing
Notes:
1. Status reads in figure are shown as asynchronous.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is
complete, and Data# Polling will output true data.
3. While in Asynchronous mode, RDY will be low while the device is in embedded erase or programming mode.
Figure 29. Data# Polling Timings (During Embedded Algorithm)
CE#
AVD#
WE#
Addresses
Data
OE#
ACC
Don't Care Don't CareA0h Don't Care
PA
PD
V
ID
1 μs
V
IL
or V
IH
t
VID
t
VIDS
WE#
CE#
OE#
t
OE
Addresses
AVD#
t
OEH
t
CE
t
CH
t
OEZ
t
CEZ
Status Data Status Data
t
ACC
VA VA
Data