80 S29WS128J/064J S29WS-J_00_A6 May 11, 2006
Data Sheet
Erase/Program Operations
Notes:
1. Not 100% tested.
2. Asynchronous mode allows both Asynchronous and Synchronous program operation. Synchronous mode allows both
Asynchronous and Synchronous program operation.
3. In asynchronous program operation timing, addresses are latched on the falling edge of WE# or rising edge of AVD#. In
synchronous program operation timing, addresses are latched on the first of either the rising edge of AVD# or the active
edge of CLK.
4. See the Erase and Programming Performance section for more information.
5. Does not include the preprogramming time.
Parameter
Description 66 MHz
80 MHz
(WS064J only)
Unit
JEDEC Standard
t
AVAV
t
WC
Write Cycle Time (Note 1) Min 45 ns
t
AVWL
t
AS
Address Setup Time (Notes 2,
3)
Synchronous
Min
4
ns
Asynchronous 0
t
WLAX
t
AH
Address Hold Time (Notes 2, 3)
Synchronous
Min
5.5
ns
Asynchronous 20
t
AVDP
AVD# Low Time Min 10 ns
t
DVWH
t
DS
Data Setup Time Min 20 ns
t
WHDX
t
DH
Data Hold Time Min 0 ns
t
GHWL
t
GHWL
Read Recovery Time Before Write Min 0 ns
t
CAS
CE# Setup Time to AVD# Min 0 ns
t
WHEH
t
CH
CE# Hold Time Min 0 ns
t
WLWH
t
WP
Write Pulse Width Min 20 ns
t
WHWL
t
WPH
Write Pulse Width High Min 20 ns
t
SR/W
Latency Between Read and Write Operations Min 0 ns
t
WHWH1
t
WHWH1
Programming Operation (Note 4) Typ <7 µs
t
WHWH1
t
WHWH1
Accelerated Programming Operation (Note 4) Typ <4 µs
t
WHWH2
t
WHWH2
Sector Erase Operation (Notes 4, 5)
Typ
<0.2
sec
Chip Erase Operation (Notes 4, 5) <104
t
VID
V
ACC
Rise and Fall Time Min 500 ns
t
VIDS
V
ACC
Setup Time (During Accelerated Programming) Min 1 µs
t
VCS
V
CC
Setup Time Min 50 µs
t
ELWL
t
CS
CE# Setup Time to WE# Min 0 ns
t
AVSW
AVD# Setup Time to WE# Min 4 ns
t
AVHW
AVD# Hold Time to WE# Min 4 ns
t
AVHC
AVD# Hold Time to CLK Min 4 ns
t
CSW
Clock Setup Time to WE# Min 5 ns