May 11, 2006 S29WS-J_00_A6 S29WS128J/064J 75
Data Sheet
Notes:
1. Figure shows total number of wait states set to four cycles. The total number of wait states can be programmed from two
cycles to seven cycles. Clock is set for active falling edge.
2. If any burst address occurs at a 64-word boundary, two additional clock cycle when wait state is set to less than 5 or
three additional clock cycle when wait state is set to 6 & 7 are inserted, clock cycle are inserted, and is indicated by RDY.
3. The device is in synchronous mode.
Figure 16. CLK Synchronous Burst Mode Read (Falling Active Clock)
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from
two cycles to seven cycles. Clock is set for active rising edge.
2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY.
3. The device is in synchronous mode.
Figure 17. Synchronous Burst Mode Read
Da
Da + 1 Da + n
OE#
Data
Addresses
Aa
AVD#
RDY
CLK
CE#
t
CES
t
ACS
t
AVC
t
AVD
t
ACH
t
OE
t
OEZ
t
CEZ
t
IACC
t
ACC
t
BDH
4 cycles for initial access shown.
t
RACC
Hi-Z
Hi-Z
Hi-Z
12345
t
RDYS
t
BACC
t
CR
Da
Da + 1 Da + n
OE#
Data
Addresses
Aa
AVD#
RDY
CLK
CE#
t
CAS
t
AAS
t
AVC
t
AVD
t
AAH
t
OE
t
RACC
t
OEZ
t
CEZ
t
IACC
t
BDH
7 cycles for initial access shown.
Hi-Z
Hi-Z Hi-Z
1234567
t
RDYS
t
BACC
t
ACC
t
CR