74 S29WS128J/064J S29WS-J_00_A6 May 11, 2006
Data Sheet
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from
two cycles to seven cycles.
2. If any burst address occurs at a 64-word boundary, two additional clock cycle when wait state is set to less than 5 or
three additional clock cycle when wait state is set to 6 & 7 are inserted, and is indicated by RDY.
3. The device is in synchronous mode.
Figure 15. CLK Synchronous Burst Mode Read (rising active CLK)
Da
Da + 1 Da + n
OE#
Data
Addresses
Aa
AVD#
RDY
CLK
CE#
t
CES
t
ACS
t
AVC
t
AVD
t
ACH
t
OE
t
RACC
t
OEZ
t
CEZ
t
IACC
t
ACC
t
BDH
7 cycles for initial access shown.
Hi-Z
Hi-Z Hi-Z
1 2 34 56 7
t
RDYS
t
BACC
t
CR