64 S29WS128J/064J S29WS-J_00_A6 May 11, 2006
Data Sheet
If the output is low (Busy), the device is actively erasing or programming. (This includes program-
ming in the Erase Suspend mode.) If the output is in high impedance (Ready), the device is in
the read mode, the standby mode, or in the erase-suspend-read mode.
Ta bl e 20, “Write Opera-
tion Status,” on page 67 shows the outputs for RDY.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or
complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read
at any address in the same bank, and is valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase operation), and during the sector erase time-
out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any ad-
dress cause DQ6 to toggle. When the operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6
toggles for approximately 100 µs, then returns to reading array data. If not all selected sectors
are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or
is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm
is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops tog
-
gling. However, the system must also use DQ2 to determine which sectors are erasing or erase-
suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling).
If a program address falls within a protected sector, DQ6 toggles for approximately 1 ms after the
program command sequence is written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embed-
ded Program algorithm is complete.
See the following for additional information: Figure 8, “Toggle Bit Algorithm,” on page 65, DQ6:
Toggle B i t I on page 64, Figure 30, “Toggle Bit Timings (During Embedded Algorithm),” on
page 87 (toggle bit timing diagram), and Tab le 19, “DQ6 and DQ2 Indications,” on page 66.
Toggle Bit I on DQ6 requires either OE# or CE# to be deasserteed and reasserted to show the
change in state.