May 11, 2006 S29WS-J_00_A6 S29WS128J/064J 63
Data Sheet
Notes:
1. VA = Valid address for programming. During a sector erase operation, a valid
address is any sector address within the sector being erased. During chip erase,
a valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change
simultaneously with DQ5.
Figure 7. Data# Polling Algorithm
RDY: Ready
The RDY is a dedicated output that, when the device is configured in the Synchronous mode, in-
dicates (when at logic low) the system should wait 1 clock cycle before expecting the next word
of data. The RDY pin is only controlled by CE#. Using the RDY Configuration Command Sequence,
RDY can be set so that a logic low indicates the system should wait 2 clock cycles before expecting
valid data.
The following conditions cause the RDY output to be low: during the initial access (in burst mode),
and after the boundary that occurs every 64 words beginning with the 64th address, 3Fh.
When the device is configured in Asynchronous Mode, the RDY is an open-drain output pin which
indicates whether an Embedded Algorithm is in progress or completed. The RDY status is valid
after the rising edge of the final WE# pulse in the command sequence.
DQ7 = Data?
Yes
No
No
DQ5 = 1?
No
Yes
Yes
FAIL
PASS
Read DQ7–DQ0
Addr = VA
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
START
