62 S29WS128J/064J S29WS-J_00_A6 May 11, 2006
Data Sheet
14. The Unlock Bypass Reset command is required to return to reading array data.
15. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase
Suspend command is valid only during a sector erase operation, and requires the bank address.
16. The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address.
17. See “Set Configuration Register Command Sequence” for details.
18. Command is valid when device is ready to read array data or when device is in autoselect mode.
19. Regardless of CLK and AVD# interaction or Control Register bit 15 setting, command mode verifies are always asynchronous read
operations.
20. ACC must be at V
HH
during the entire operation of this command
21. The fourth cycle programs the addressed locking bit. The fifth and sixth cycles are used to validate whether the bit has been fully
programmed. If DQ0 (in the sixth cycle) reads 0, the program command must be issued and verified again.
22. The fourth cycle erases all PPBs. The fifth and sixth cycles are used to validate whether the bits have been fully erased. If DQ0 (in the sixth
cycle) reads 1, the erase command must be issued and verified again.
23. The entire four bus-cycle sequence must be entered for each portion of the password.
24. Before issuing the erase command, all PPBs should be programmed in order to prevent over-erasure of PPBs.
25. In the fourth cycle, 01h indicates PPB set; 00h indicates PPB not set.
Write Operation Status
The device provides several bits to determine the status of a program or erase operation: DQ2,
DQ3, DQ5, DQ6, and DQ7.
Tab le 20, “Write Operation Status,” on page 67 and the following sub-
sections describe the function of these bits. DQ7 and DQ6 each offers a method for determining
whether a program or erase operation is complete or in progress.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase
algorithm is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is
valid after the rising edge of the final WE# pulse in the command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the
datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend.
When the Embedded Program algorithm is complete, the device outputs the datum programmed
to DQ7. The system must provide the program address to read valid status information on DQ7.
If a program address falls within a protected sector, Data# Polling on DQ7 is active for approxi
-
mately 1 µs, then that bank returns to the read mode.
During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embed-
ded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling
produces a “1” on DQ7. The system must provide an address within any of the sectors selected
for erasure to read valid status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected,
Data# Polling on DQ7 is active for approximately 100 µs, then the bank returns to the read mode.
If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7
at an address within a protected sector, the status may not be valid.
Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asyn-
chronously with DQ6–DQ0 while Output Enable (OE#) is asserted low. That is, the device may
change from providing status information to valid data on DQ7. Depending on when the system
samples the DQ7 output, it may read the status or valid data. Even if the device has completed
the program or erase operation and DQ7 has valid data, the data outputs on DQ6-DQ0 may be
still invalid. Valid data on DQ7-D00 will appear on successive read cycles.
Tabl e 20, “Write Operation Status,” on page 67 shows the outputs for Data# Polling on DQ7.
Figure 7, “Data# Polling Algorithm,” on page 63 shows the Data# Polling algorithm. Figure 29,
“Data# Polling Timings (During Embedded Algorithm),” on page 86 in the AC Characteristics sec-
tion shows the Data# Polling timing diagram.
