May 11, 2006 S29WS-J_00_A6 S29WS128J/064J 55
Data Sheet
The host system may also initiate the chip erase command sequence while the device is in the
unlock bypass mode. The command sequence is two cycles cycles in length instead of six cycles.
See
Tabl e 18, “Command Definitions,” on page 60 for details on the unlock bypass command
sequences.
Figure 6, “Erase Operation,” on page 56 illustrates the algorithm for the erase operation. Refer to
the Erase/Program Operations table in the AC Characteristics section for parameters and timing
diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writ-
ing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written,
and are then followed by the address of the sector to be erased, and the sector erase command.
Ta bl e 18, “Command Definitions,” on page 60 shows the address and data requirements for the
sector erase command sequence.
The device does not require the system to preprogram prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the entire memory for an all zero data pattern prior to
electrical erase. The system is not required to provide any controls or timings during these
operations.
After the command sequence is written, a sector erase time-out of no less than 50 µs occurs.
During the time-out period, additional sector addresses and sector erase commands may be writ
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ten. Loading the sector erase buffer may be done in any sequence, and the number of sectors
may be from one sector to all sectors. The time between these additional cycles must be less than
50 µs, otherwise erasure may begin. Any sector erase address and command following the ex
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ceeded time-out may or may not be accepted. It is recommended that processor interrupts be
disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled
after the last Sector Erase command is written. If any command other than 30h, B0h, F0h is input
during the time-out period, the normal operation will not be guaranteed.
The system can monitor DQ3 to determine if the sector erase timer has timed out (See “DQ3:
Sector Erase Timer” section on page 67.) The time-out begins from the rising edge of the final
WE# pulse in the command sequence.
When the Embedded Erase algorithm is complete, the bank returns to reading array data and ad-
dresses are no longer latched. Note that while the Embedded Erase operation is in progress, the
system can read data from the non-erasing bank. The system can determine the status of the
erase operation by reading DQ7 or DQ6/DQ2 in the erasing bank. Refer to the
“Write Operation
Status” section on page 62 for information on these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other
commands are ignored. However, note that a hardware reset immediately terminates the erase
operation. If that occurs, the sector erase command sequence should be reinitiated once that
bank has returned to reading array data, to ensure data integrity.
The host system may also initiate the sector erase command sequence while the device is in the
unlock bypass mode. The command sequence is four cycles cycles in length instead of six cycles.
Figure 6, “Erase Operation,” on page 56 illustrates the algorithm for the erase operation. Refer to
the Erase/Program Operations table in the AC Characteristics on page 72 for parameters and tim-
ing diagrams.
Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and
then read data from, or program data to, any sector not selected for erasure. The bank address
is required when writing this command. This command is valid only during the sector erase op
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