54 S29WS128J/064J S29WS-J_00_A6 May 11, 2006
Data Sheet
Figure 5, “Program Operation,” on page 54 illustrates the algorithm for the program operation.
Refer to the Erase/Program Operations table in the AC Characteristics section for parameters, and
Figure 23, “Asynchronous Program Operation Timings: AVD# Latched Addresses,” on page 81
and Figure 25, “Synchronous Program Operation Timings: WE# Latched Addresses,” on page 83
for timing diagrams.
Note: See Table 18 for program command sequence.
Figure 5. Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing
two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then
followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The
device does not require the system to preprogram prior to erase. The Embedded Erase algorithm
automatically preprograms and verifies the entire memory for an all zero data pattern prior to
electrical erase. The system is not required to provide any controls or timings during these oper
-
ations. Tab le 18, “Command Definitions,” on page 60 shows the address and data requirements
for the chip erase command sequence.
When the Embedded Erase algorithm is complete, that bank returns to the read mode and ad-
dresses are no longer latched. The system can determine the status of the erase operation by
using DQ7 or DQ6/DQ2. Refer to the
“Write Operation Status” section on page 62 for information
on these status bits.
Any commands written during the chip erase operation are ignored. However, note that a hard-
ware reset immediately terminates the erase operation. If that occurs, the chip erase command
sequence should be reinitiated once that bank has returned to reading array data, to ensure data
integrity.
START
Write Program
Command Sequence
Data Poll
from System
Verify Data?
No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
