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WS064J0SBFW00

WS064J0SBFW00首页预览图
型号: WS064J0SBFW00
PDF文件:
  • WS064J0SBFW00 PDF文件
  • WS064J0SBFW00 PDF在线浏览
功能描述: 128/64 Megabit (8/4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
PDF文件大小: 2245.3 Kbytes
PDF页数: 共97页
制造商: SPANSION[SPANSION]
制造商LOGO: SPANSION[SPANSION] LOGO
制造商网址: http://www.spansion.com
捡单宝WS064J0SBFW00
PDF页面索引
120%
May 11, 2006 S29WS-J_00_A6 S29WS128J/064J 49
Data Sheet
Ta b l e 1 4 . Programmable Wait State Settings
Notes:
1. Upon power-up or hardware reset, the default setting is seven wait states.
2. RDY will default to being active with data when the Wait State Setting is set to a
total initial access cycle of 2.
It is recommended that the wait state command sequence be written, even if the default wait
state value is desired, to ensure the device is set as expected. A hardware reset will set the wait
state to the default setting.
Standard wait-state Handshaking Option
The host system must set the appropriate number of wait states in the flash device depending
upon the clock frequency. The host system should set address bits A14–A12 to 010 for a clock
frequency of 66/80 MHz for the system/device to execute at maximum speed.
Ta bl e 15 describes the recommended number of clock cycles (wait states) for various conditions.
Ta b l e 1 5 . Wait States for Standard wait-state Handshaking
Notes:
1. In the 8-, 16- and 32-word burst read modes, the address pointer does not cross
64-word boundaries (addresses which are multiples of 3Fh).
2. For WS128J model numbers 10 and 11, an additional clock cycle is required for
boundary crossings while in Continuous read mode.
The host system must set the appropriate number of wait states in the flash device depending
upon the clock frequency. Note that the host system must set again the number of wait state
when the host system change the clock frequency. For example, the host system must set from
6 or 7 wait state to less than 5 wait states when the host system change the clock frequency from
80MHz to less than 80MHz. The autoselect function allows the host system to determine whether
the flash device is enabled for handshaking. See the
Autoselect Command Sequence” section on
page 51 for more information.
A14 A13 A12 Total Initial Access Cycles
0 0 0 2
0 0 1 3
0 1 0 4
0 1 1 5
1 0 0 6
1 0 1 7 (default)
1 1 0 Reserved
1 1 1 Reserved
Burst Mode
Typical No. of Clock Cycles after AVD# Low
66 MHz 80 MHz
8-Word or 16-Word or Continuous 4 6 or 7
32-Word 5 7
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