May 11, 2006 S29WS-J_00_A6 S29WS128J/064J 47
Data Sheet
See also “Requirements for Asynchronous ReadOperation (Non-Burst)” section on page 14 and
“Requirements for Synchronous (Burst) Read Operation” section on page 14 for more information.
The Asynchronous Read and Synchronous/Burst Read tables provide the read parameters, and
Figure 15, “CLK Synchronous Burst Mode Read (rising active CLK),” on page 74, Figure 17, “Syn-
chronous Burst Mode Read,” on page 75, and Figure 20, “Asynchronous Mode Read with Latched
Addresses,” on page 77 show the timings.
Set Configuration Register Command Sequence
The device uses a configuration register to set the various burst parameters: number of wait
states, burst read mode, active clock edge, RDY configuration, and synchronous mode active. The
configuration register must be set before the device will enter burst mode.
The configuration register is loaded with a three-cycle command sequence. The first two cycles
are standard unlock sequences. On the third cycle, the data should be C0h, address bits A11–A0
should be 555h, and address bits A19–A12 set the code to be latched. The device will power up
or after a hardware reset with the default setting, which is in asynchronous mode. The register
must be set before the device can enter synchronous mode. The configuration register can not
be changed during device operations (program, erase, or sector lock).
