16 S29WS128J/064J S29WS-J_00_A6 May 11, 2006
Data Sheet
As an example: if the starting address in the 8-word mode is 39h, the address range to be read
would be 38-3Fh, and the burst sequence would be 39-3A-3B-3C-3D-3E-3F-38h-etc. The burst
sequence begins with the starting address written to the device, but wraps back to the first ad
-
dress in the selected group. In a similar fashion, the 16-word and 32-word Linear Wrap modes
begin their burst sequence on the starting address written to the device, and then wrap back to
the first address in the selected address group. Note that in these three burst read modes
the address pointer does not cross the boundary that occurs every 128 or 64 words;
thus, no wait states are inserted (except during the initial access).
The RDY pin indicates when data is valid on the bus.
Configuration Register
The device uses a configuration register to set the various burst parameters: number of wait
states, burst read mode, active clock edge, RDY configuration, and synchronous mode active.
Handshaking
The device is equipped with a handshaking feature that allows the host system to simply monitor
the RDY signal from the device to determine when the initial word of burst data is ready to be
read. The host system should use the programmable wait state configuration to set the number
of wait states for optimal burst mode operation. The initial word of burst data is indicated by the
active edge of RDY after OE# goes low.
For optimal burst mode performance, the host system must set the appropriate number of wait
states in the flash device depending on clock frequency. See
“Set Configuration Register Com-
mand Sequence” section on page 47 for more information.
Simultaneous Read/Write Operations with Zero Latency
This device is capable of reading data from one bank of memory while programming or erasing
in another bank of memory. An erase operation may also be suspended to read from or program
to another location within the same bank (except the sector being erased).
Figure 38, “Back-to-
Back Read/Write Cycle Timings,” on page 92 shows how read and write cycles may be initiated
for simultaneous operation with zero latency. Refer to the DC Characteristics table for read-while-
program and read-while-erase current specifications.
Writing Commands/Command Sequences
The device has the capability of performing an asynchronous or synchronous write operation.
While the device is configured in Asynchronous read mode, it is able to perform Asynchronous
write operations only. CLK is ignored in the Asynchronous programming mode. When in the Syn
-
chronous read mode configuration, the device is able to perform both Asynchronous and
Synchronous write operations. CLK and WE# address latch is supported in the Synchronous pro
-
gramming mode. During a synchronous write operation, to write a command or command
sequence (which includes programming data to the device and erasing sectors of memory), the
system must drive AVD# and CE# to V
IL
, and OE# to V
IH
when providing an address to the de-
vice, and drive WE# and CE# to V
IL
, and OE# to V
IH
. when writing commands or data. During an
asynchronous write operation, the system must drive CE# and WE# to V
IL
and OE# to V
IH
when
providing an address, command, and data. Addresses are latched on the last falling edge of WE#
or CE#, while data is latched on the 1st rising edge of WE# or CE#. The asynchronous and syn
-
chronous programing operation is independent of the Set Device Read Mode bit in the
Configuration Register (see
Tab le 17, “Configuration Register,” on page 51).
The device features an Unlock Bypass mode to facilitate faster programming. Once the device en-
ters the Unlock Bypass mode, only two write cycles are required to program a word, instead of
four.
