14 S29WS128J/064J S29WS-J_00_A6 May 11, 2006
Data Sheet
Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated
through the internal command register. The command register itself does not occupy any addres
-
sable memory location. The register is composed of latches that store the commands, along with
the address and data information needed to execute the command. The contents of the register
serve as inputs to the internal state machine. The state machine outputs dictate the function of
the device.
Ta b l e 1 lists the device bus operations, the inputs and control levels they require, and
the resulting output. The following subsections describe each of these operations in further detail.
Ta b l e 1. Device Bus Operations
Legend: L = Logic 0, H = Logic 1, X = Don’t Care
Note: Default active edge of CLK is the rising edge.
Requirements for Asynchronous ReadOperation (Non-Burst)
To read data from the memory array, the system must first assert a valid address on Amax–
A0(A22-A0 for WS128J and A21-A0 for WS064J), while driving AVD# and CE# to V
IL
. WE# should
remain at V
IH
. The rising edge of AVD# latches the address. The data will appear on DQ15–DQ0.
Since the memory array is divided into four banks, each bank remains enabled for read access
until the command register contents are altered.
Address access time (t
ACC
) is equal to the delay from stable addresses to valid output data. The
chip enable access time (t
CE
) is the delay from the stable addresses and stable CE# to valid data
at the outputs. The output enable access time (t
OE
) is the delay from the falling edge of OE# to
valid data at the output.
The internal state machine is set for reading array data in asynchronous mode upon device
power-up, or after a hardware reset. This ensures that no spurious alteration of the memory con
-
tent occurs during the power transition.
Requirements for Synchronous (Burst) Read Operation
The device is capable of continuous sequential burst operation and linear burst operation of a pre-
set length. When the device first powers up, it is enabled for asynchronous read operation.
Operation CE# OE# WE# A22–0 DQ15–0 RESET#
CLK
(See Note)
AVD#
Asynchronous Read - Addresses Latched L L H Addr In I/O H X
Asynchronous Read - Addresses Steady State L L H Addr In I/O H X L
Asynchronous Write L H L Addr In I/O H X L
Synchronous Write L H L Addr In I/O H
Standby (CE#) HX XHIGH ZHIGH Z H X X
Hardware Reset XX XHIGH ZHIGH Z L X X
Burst Read Operations
Load Starting Burst Address L X H Addr In X H
Advance Burst to next address with appropriate Data
presented on the Data Bus
LLHHIGH Z
Burst
Data Out
HH
Terminate current Burst read cycle HX HHIGH ZHIGH Z H X
Terminate current Burst read cycle via RESET# XXHHIGH ZHIGH Z L X X
Terminate current Burst read cycle and start new
Burst read cycle
LXHHIGH ZI/O H
