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WM8716_06

WM8716_06首页预览图
型号: WM8716_06
PDF文件:
  • WM8716_06 PDF文件
  • WM8716_06 PDF在线浏览
功能描述: High Performance 24-bit, 192kHz Stereo DAC
PDF文件大小: 334.37 Kbytes
PDF页数: 共27页
制造商: WOLFSON[Wolfson Microelectronics plc]
制造商LOGO: WOLFSON[Wolfson Microelectronics plc] LOGO
制造商网址: http://www.wolfsonmicro.com
捡单宝WM8716_06
PDF页面索引
120%
Product ion Data WM8716
w PD Rev 4.1September 2006
15
SOFT MUTE
MUT
(REG2, B0)
L
Soft Mute off (normal operation)
H
Soft Mute on (no output)
Table 8 Soft Mute
Settin g MUT causes the attenuation to ramp f rom t he current value down to 00. The values held in
the at tenuat ion regis ters ar e unc hanged. When MUT is reset the at tenuation will ramp bac k up to the
previous value. The ram p rate is 128/fs s /0. 5dB st ep.
DIG ITAL DE- E M PHASIS
DEM
(REG2, B1)
L
De-emphasis off
H
De-emphasis on
Table 9 Digital De-Emphasis
DAC OPERATION ENABLE
OPE
(REG2,B2)
L
Normal operat ion
H
DAC output forced to bipolar zero,
irrespective of input data.
Table 10 DAC Operation Enabl e
AUDIO DATA INPUT FORMAT
I2S
(REG3, B0)
IW1
(REG2, B4)
IW0
(REG2, B3)
AUD IO IN TERFACE
0 0 0
16-bit st andard right jus t if i ed
0 0 1 20-bit standard right jus t if i ed
0 1 0
24-bit st andard right jus t if i ed
0 1 1
24-bit left justified (MSB first)
1 0 0
16-bit I
2
S
1 0 1 24-bit I
2
S
1 1 0
20-bit I
2
S
1 1 1
20-bit left justified (MSB first)
Table 11 Audio Data Input Format
POLA RITY OF LR INPUT CLOCK
The left c hannel data for a partic ular s ample inst ant is always input first, then the ri ght channel dat a.
LRP
(REG3, B1)
L
LR High – left channel
LR Low – right channel
H
LR Low – left channel
LR High – right channel
Table 12 Polarity of LR Input Clock
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