WM8716 Production Data
w PD Rev 4.1 September 2006
14
REGISTER BITS NAME DEFAULT DESCRIPTION
[7:0] AL[7:0] FF
Attenuation data for left channel.
0
8 LDL 0
Attenuation data load control for left channel.
[7:0] AR[7:0] FF
Attenuation data for right channel.
1
8 LDR 0
Attenuation data load control for right channel.
0 MUT 0
Left and right DACs soft mute control.
1 DEM 0
De-emphas is c ontrol.
2 OPE 0
Left and right DACs operation control.
2
[4:3] IW[1:0] 0
Input audio data bit selec t .
0 I2S 0
Audio data form at selec t .
1 LRP 0
Polarity of LRCIN select.
2 ATC 0
Attenuator control.
3 SR0 0
Digital filt er slow roll-off selec t.
4 REV 0
Output phase reverse.
5 CKO 0
CLKO frequency select .
[7:6] SF[1:0] 0
Sampling rate select.
3
8 IZD 0
Infinite zero detection circuit control.
[5:4] DIFF 0
Differenti al output m ode.
4
6 CDD 0 Clock loss detector disable.
Table 6 Register Bit Descriptions
DAC OUTPUT ATTENUATION
The level of attenuation for eight bit code X, is given by:
0.5 ∗ (X - 255) dB, 1 ≤ X ≤ 255
- ∞dB (mute), X = 0
Bit 8 in register 0 (LDL) is used to cont rol the l oading of att enuation data i n B[7:0] . W hen LDL is s et
to 0, attenuation data will be loaded into AL[7:0], but it will not affect the filter attenuation. LDR in
regist er 1 has the s ame funct ion for r ight c hannel at tenuation. Only when LDL or LDR is set to '1' will
the filter attenuation be updated. This permits left and right channel attenuation to be updated
simultaneously.
Attenuation level is controlled by AL[7:0] (left channel) or AR[7:0] (right channel). Attenuation levels
are given in Table 4.
X[7:0] ATTENUATION LEVEL
00(hex) - ∞dB (mute)
01(hex) -127.0dB
: :
: :
FD(hex) -1.0dB
FE(hex) -0.5dB
FF(hex) 0.0dB
Table 7 Attenuation Contro l Level
Bit 2 in Reg3 is used to control the attenuator (ATC). When ATC is “high”, the attenuation data
loaded in program register 0 is used for both the left and the right channels. W hen ATC is low, the
attenuat ion data for each regis ter is appli ed separatel y to lef t and right channels .
