White Electronic Designs
February 2005
Rev. 3
WEDPN16M72V-XB2X
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
WRITE
The WRITE command is used to initiate a burst write
access to an active row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0-8
selects the starting column location. The value on input A10
determines whether or not AUTO PRECHARGE is used. If
AUTO PRECHARGE is selected, the row being accessed
will be precharged at the end of the WRITE burst; if AUTO
PRECHARGE is not selected, the row will remain open for
subsequent accesses. Input data appearing on the I/Os
is written to the memory array subject to the DQM input
logic level appearing coincident with the data. If a given
DQM signal is registered LOW, the corresponding data
will be written to memory; if the DQM signal is registered
HIGH, the corresponding data inputs will be ignored, and a
WRITE will not be executed to that byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the
open row in a particular bank or the open row in all banks.
The bank(s) will be available for a subsequent row access
a specifi ed time (t
RP
) after the PRECHARGE command is
issued. Input A10 determines whether one or all banks are
to be precharged, and in the case where only one bank
is to be precharged, inputs BA0, BA1 select the bank.
Otherwise BA0, BA1 are treated as “Don’t Care.” Once a
bank has been precharged, it is in the idle state and must
be activated prior to any READ or WRITE commands being
issued to that bank.
AUTO PRECHARGE
AUTO PRECHARGE is a feature which performs the
same individual-bank PRECHARGE function described
above, without requiring an explicit command. This is
accomplished by using A10 to enable AUTO PRECHARGE
in conjunction with a specifi c READ or WRITE command.
A precharge of the bank/row that is addressed with the
READ or WRITE command is automatically performed
upon completion of the READ or WRITE burst, except in
the full-page burst mode, where AUTO PRECHARGE does
not apply. AUTO PRECHARGE is nonpersistent in that it
is either enabled or disabled for each individual READ or
WRITE command.
AUTO PRECHARGE ensures that the precharge is
initiated at the earliest valid stage within a burst. The user
must not issue another command to the same bank until
the precharge time (t
RP
) is completed. This is determined
as if an explicit PRECHARGE command was issued at
the earliest possible time.
BURST TERMINATE
The BURST TERMINATE command is used to truncate
either fi xed-length or full-page bursts. The most recently
registered READ or WRITE command prior to the BURST
TERMINATE command will be truncated.
AUTO REFRESH
AUTO REFRESH is used during normal operation of
the SDRAM and is analagous to CAS#-BEFORE-RAS#
(CBR) REFRESH in conventional DRAMs. This command
is nonpersistent, so it must be issued each time a refresh
is required.
The addressing is generated by the internal refresh
controller. This makes the address bits “Don’t Care” during
an AUTO REFRESH command. Each 256Mb SDRAM
requires 8,192 AUTO REFRESH cycles every refresh
period (t
REF
). Providing a distributed AUTO REFRESH
command will meet the refresh requirement and ensure
that each row is refreshed. Alternatively, 8,192 AUTO
REFRESH commands can be issued in a burst at the
minimum cycle rate (t
RC
), once every refresh period
(t
REF
).
SELF REFRESH*
The SELF REFRESH command can be used to retain data
in the SDRAM, even if the rest of the system is powered
down. When in the self refresh mode, the SDRAM retains
data without external clocking. The SELF REFRESH
command is initiated like an AUTO REFRESH command
except CKE is disabled (LOW). Once the SELF REFRESH
command is registered, all the inputs to the SDRAM
become “Don’t Care,” with the exception of CKE, which
must remain LOW.
Once self refresh mode is engaged, the SDRAM provides
its own internal clocking, causing it to perform its own
AUTO REFRESH cycles. The SDRAM must remain in
self refresh mode for a minimum period equal to tRAS and
may remain in self refresh mode for an indefi nite period
beyond that.
The procedure for exiting self refresh requires a sequence
of commands. First, CLK must be stable (stable clock
is defi ned as a signal cycling within timing constraints
specified for the clock pin) prior to CKE going back
HIGH. Once CKE is HIGH, the SDRAM must have NOP
commands issued (a minimum of two clocks) for t
XSR
,
because time is required for the completion of any internal
refresh in progress.
