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WEDPN16M72V-125B2C

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型号: WEDPN16M72V-125B2C
PDF文件:
  • WEDPN16M72V-125B2C PDF文件
  • WEDPN16M72V-125B2C PDF在线浏览
功能描述: 16Mx72 Synchronous DRAM
PDF文件大小: 442.21 Kbytes
PDF页数: 共14页
制造商: WEDC[White Electronic Designs Corporation]
制造商LOGO: WEDC[White Electronic Designs Corporation] LOGO
制造商网址: http://www.whiteedc.com
捡单宝WEDPN16M72V-125B2C
PDF页面索引
120%
White Electronic Designs
February 2005
Rev. 3
WEDPN16M72V-XB2X
11
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
NOTES:
1. All voltages referenced to VSS.
2. This parameter is not tested but guaranteed by design. f = 1 MHz, T
A = 25°C.
3. I
DD is dependent on output loading and cycle rates. Specifi ed values are obtained
with minimum cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifi cations are used only to indicate cycle time at which proper
operation over the full temperature range is ensured.
6. An initial pause of 100µs is required after power-up, followed by two AUTO
REFRESH commands, before proper device operation is ensured. (V
CC must be
powered up simultaneously.) The two AUTO REFRESH command wake-ups should
be repeated any time the t
REF refresh requirement is exceeded.
7. AC characteristics assume t
T = 1ns.
8. In addition to meeting the transition rate specifi cation, the clock and CKE must
transit between V
IH and VIL (or between VIL and VIH) in a monotonic manner.
9. Outputs measured at 1.5V with equivalent load:
Q
1.5V
50Ω
10. tHZ defi nes the time at which the output achieves the open circuit condition; it is not
a reference to V
OH or VOL. The last valid data element will meet tOH before going
High-Z.
11. AC timing and I
DD tests have VIL = 0V and VIH = 3V, with timing referenced to 1.5V
crossover point.
12. Other input signals are allowed to transition no more than once every two clocks
and are otherwise at valid
VIH or VIL levels.
13. I
CC specifi cations are tested after the device is properly initialized.
14. Timing actually specifi ed by t
CKS; clock(s) specifi ed as a reference only at minimum
cycle rate.
15. Timing actually specifi ed by t
WR plus tRP; clock(s) specifi ed as a reference only at
minimum cycle rate.
16. Timing actually specifi ed by t
WR.
17. Required clocks are specifi ed by JEDEC functionality and are not dependent on
any timing parameter.
18. The I
CC current will decrease as the CAS latency is reduced. This is due to the fact
that the maximum cycle rate is slower as the CAS latency is reduced.
19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
21. V
IH overshoot: VIH (MAX) = VCC + 2V for a pulse width 3ns, and the pulse width
cannot be greater than one third of the cycle rate. V
IL undershoot: VIL (MIN) = -2V
for a pulse width 3ns.
22. The clock frequency must remain constant (stable clock is defi ned as a signal
cycling within timing constraints specifi ed for the clock pin) during access or
precharge states (READ, WRITE, including t
WR, and PRECHARGE commands).
CKE may be used to reduce the data rate.
23. Auto precharge mode only. The precharge timing budget (t
RP) begins 7.5ns/7ns
after the fi rst clock delay, after the last WRITE is executed.
24. Precharge mode only.
25. JEDEC and PC100 specify three clocks.
26. Parameter guaranteed by design.
27. Self refresh available in commercial and industrial temperatures only.
AC FUNCTIONAL CHARACTERISTICS (NOTES 5,6,7,8,9,11)
Parameter/Condition Symbol -100 -125 -133 Units
READ/WRITE command to READ/WRITE command (17) t
CCD
111t
CK
CKE to clock disable or power-down entry mode (14) t
CKED
1 1 1 t
CK
CKE to clock enable or power-down exit setup mode (14) t
PED
111t
CK
DQM to input data delay (17) t
DQD
0 0 0 t
CK
DQM to data mask during WRITEs t
DQM
0 0 0 t
CK
DQM to data high-impedance during READs t
DQZ
2 2 2 t
CK
WRITE command to input data delay (17) t
DWD
0 0 0 t
CK
Data-in to ACTIVE command (15) t
DAL
455t
CK
Data-in to PRECHARGE command (16) t
DPL
2 2 2 t
CK
Last data-in to burst STOP command (17) t
BDL
111t
CK
Last data-in to new READ/WRITE command (17) t
CDL
1 1 1 t
CK
Last data-in to PRECHARGE command (16) t
RDL
2 2 2 t
CK
LOAD MODE REGISTER command to ACTIVE or REFRESH command (25) t
MRD
222t
CK
Data-out to high-impedance from PRECHARGE command (17)
CL = 3 t
ROH
333t
CK
CL = 2 t
ROH
2—t
CK
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