W9412G6CH
Publication Release Date: Jul. 04, 2007
- 7 - Revision A06
5. PIN DESCRIPTION
PIN NUMBER
PIN
NAME
FUNCTION DESCRIPTION
28 − 32,
35 − 41
A0 − A11
Address
Multiplexed pins for row and column address.
Row address: A0 − A11.
Column address: A0 − A8. (A10 is used for Auto-precharge)
26, 27 BS0, BS1 Bank Select
Select bank to activate during row address latch time, or
bank to read/write during column address latch time.
2, 4, 5, 7, 8, 10,
11, 13, 54, 56, 57,
59, 60, 62, 63, 65
DQ0 −
DQ15
Data Input/ Output
The DQ0 – DQ15 input and output data are synchronized
with both edges of DQS.
16,51
LDQS,
UDQS
Data Strobe
DQS is Bi-directional signal. DQS is input signal during write
operation and output signal during read operation. It is Edge-
aligned with read data, Center-aligned with write data.
24
CS
Chip Select
Disable or enable the command decoder. When command
decoder is disabled, new command is ignored and previous
operation continues.
23, 22, 21
RAS
,
CAS ,
WE
Command Inputs
Command inputs (along with
CS
) define the command
being entered.
20, 47 LDM, UDM Write Mask
When DM is asserted “high” in burst write, the input data is
masked. DM is synchronized with both edges of DQS.
45, 46
CLK,
CLK
Differential Clock
Inputs
All address and control input signals are sampled on the
crossing of the positive edge of CLK and negative edge of
CLK .
44 CKE Clock Enable
CKE controls the clock activation and deactivation. When
CKE is low, Power Down mode, Suspend mode, or Self
Refresh mode is entered.
49 VREF Reference Voltage VREF is reference voltage for inputs.
1, 18, 33 VDD Power (+2.5V) Power for logic circuit inside DDR SDRAM.
34, 48, 66 VSS Ground Ground for logic circuit inside DDR SDRAM.
3, 9, 15, 55, 61 VDDQ
Power (+2.5V) for
I/O Buffer
Separated power from V
DD, used for output buffer, to
improve noise.
6, 12, 52, 58, 64 VSSQ
Ground for I/O
Buffer
Separated ground from V
SS, used for output buffer, to
improve noise.
14, 17, 19, 25,
42, 43, 50, 53
NC1 No Connection
No connection
(NC pin should be connected to GND or
floating)
