W9412G6CH
Publication Release Date: Jul. 04, 2007
- 47 - Revision A06
11.13 Read Interrupted by Write & BST (BL = 8)
READ
CMD
DQS
DQ
CLK
CLK
BST
Q0 Q1 Q2 Q3 Q4 Q5
CAS Latency = 2
WRIT
D0 D1 D2 D3 D4 D5 D6 D7
Burst Read cycle must be terminated by BST Command to avoid I/O conflict.
11.14 Read Interrupted by Precharge (BL = 8)
READ
CMD
DQS
DQ
CLK
CLK
PRE
Q0 Q1 Q2 Q3 Q4 Q5
Q0 Q1 Q2 Q3 Q4 Q5
CAS Latency
CAS Latency
CAS Latency = 2
DQS
DQ
CAS Latency = 3