W9412G6CH
Publication Release Date:Jul. 04, 2007
- 4 - Revision A06
1. GENERAL DESCRIPTION
W9412G6CH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR
SDRAM); organized as 2M words × 4 banks × 16 bits. Using pipelined architecture and 0.11µm
process technology, W9412G6CH delivers a data bandwidth of up to 444M words per second (-45).
To fully comply with the personal computer industrial standard, W9412G6CH is sorted into four speed
grades: -45, -5, -6 and -75 .The -45 is compliant to the DDR444/CL3 specification, the -5 is compliant
to the DDR400/CL3 specification, the -6 is compliant to the DDR333/CL2.5 specification and the -75 is
compliant to the DDR266/CL2 specification.
All Input reference to the positive edge of CLK (except for DQ, DM and CKE). The timing reference
point for the differential clock is when the CLK and
CLK signals cross during a transition. Write and
Read data are synschronized with the both edges of DQS (Data Strobe).
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W9412G6CH is ideal for main memory in
high performance applications.
2. FEATURES
• 2.5V ±0.2V Power Supply for DDR266
• 2.5V ±0.2V Power Supply for DDR333
• 2.6V ± 5% Power Supply for DDR400
• 2.6V ± 5% Power Supply for DDR444
• Up to 222 MHz Clock Frequency
• Double Data Rate architecture; two data transfers per clock cycle
• Differential clock inputs (CLK and
CLK )
• DQS is edge-aligned with data for Read; center-aligned with data for Write
• CAS Latency: 2, 2.5 and 3
• Burst Length: 2, 4 and 8
• Auto Refresh and Self Refresh
• Precharged Power Down and Active Power Down
• Write Data Mask
• Write Latency = 1
• 15.6µS Refresh interval (4K / 64 mS Refresh)
• Maximum burst refresh cycle: 8
• Interface: SSTL_2
• Packaged in TSOP II 66-pin, 400 mil, 0.65 mm pin pitch, using Pb free with RoHS compliant
