W9412G6CH
Publication Release Date: Jul. 04, 2007
- 31 - Revision A06
CLK
CLK
V
SS
V
ICK
V
X
V
X
V
X
V
X
V
X
V
ICK
V
ICK
V
ICK
V
ID(AC)
V
ID(AC)
0 V Differential
V
ISO
V
ISO(min)
V
ISO(max)
V
SS
(16) tAC and tDQSCK depend on the clock jitter. These timing are measured at stable clock.
(17) A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device..
