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W9412G6CH

W9412G6CH首页预览图
型号: W9412G6CH
PDF文件:
  • W9412G6CH PDF文件
  • W9412G6CH PDF在线浏览
功能描述: 2M × 4 BANKS × 16 BITS DDR SDRAM
PDF文件大小: 1636.45 Kbytes
PDF页数: 共55页
制造商: WINBOND[Winbond]
制造商LOGO: WINBOND[Winbond] LOGO
制造商网址: http://www.winbond.com
捡单宝W9412G6CH
PDF页面索引
120%
W9412G6CH
Publication Release Date:Jul. 04, 2007
- 26 - Revision A06
9.5 DC Characteristics
MAX.
SYM. PARAMETER
-45 -5 -6 -75
UNIT NOTES
IDD0
Operating current: One Bank Active-Precharge; tRC = tRC min;
t
CK = tCK min; DQ, DM and DQS inputs changing twice per
clock cycle; Address and control inputs changing once per
clock cycle
130 130 120 110 mA 7
IDD1
Operating current: One Bank Active-Read-Precharge; Burst =
2; t
RC = tRC min; CL = 3; tCK = tCK min; IOUT = 0 mA; Address
and control inputs changing once per clock cycle.
140 140 130 120 7, 9
IDD2P
Precharge Power Down standby current: All Banks Idle; Power
down mode; CKE <
VIL max; tCK = tCK min; Vin = VREF for DQ,
DQS and DM
20 20 20 20
IDD2N
Idle standby current: CS > VIH min; All Banks Idle; CKE >
V
IH min; tCK = tCK min; Address and other control inputs
changing once per clock cycle; Vin >
VIH min or Vin < VIL max
for DQ, DQS and DM
45 45 45 45 7
IDD3P
Active Power Down standby current: One Bank Active; Power
down mode; CKE <
VIL max; tCK = tCK min
20 20 20 20
IDD3N
Active standby current: CS > VIH min; CKE > VIH min; One
Bank Active-Precharge; t
RC = tRAS max; tCK = tCK min; DQ, DM
and DQS inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle
60 60 60 60 7
IDD4R
Operating current: Burst = 2; Reads; Continuous burst; One
Bank Active; Address and control inputs changing once per
clock cycle; CL=3; t
CK = tCK min; IOUT = 0mA
180 180 170 160 7, 9
IDD4W
Operating current: Burst = 2; Write; Continuous burst; One
Bank Active; Address and control inputs changing once per
clock cycle; CL = 3; t
CK = tCK min; DQ, DM and DQS inputs
changing twice per clock cycle
180 180 170 160 7
IDD5
Auto Refresh current: tRC = tRFC min 200 200 190 180 7
IDD6
Self Refresh current: CKE < 0.2V 3 3 3 3
IDD7
Random Read current: 4 Banks Active Read with activate
every 20nS, Auto-Precharge Read every 20 nS; Burst = 4;
t
RCD = 3; IOUT = 0mA; DQ, DM and DQS inputs changing twice
per clock cycle; Address changing once per clock cycle
320 320 300 280
CK
CK
DQS
RANDOM READ CURRENT Timing
t
RCD
t
RC
t
CK = 10ns
(
I
DD7)
Bank 0
Row d
Bank 3
Row c
Bank 1
Row e
Bank 1
Row e
ADDRESS
Bank 0
Row d
Bank 2
Row f
Bank 3
Row q
Bank 2
Col f
READ
AP
ACT
READ
AP
COMMAND
READ
AP
ACT
ACT
READ
AP
ACT
DQ
Qa Qb
Qb
Qb
Qb
Qc Qc Qc
Qc
Qd Qd Qd
Qd
Qe
QeQa
Bank 0
Row h
ACT
Bank 0
Col d
READ
AP
ACTACTACT ACT
Bank 1
Col e
Bank 2
Row f
Bank 3
Row q
Bank 2
Col f
Bank 0
Row h
READ
AP
Bank 1
Row e
Bank 3
Col c
Bank 0
Row d
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