W9412G6CH
Publication Release Date:Jul. 04, 2007
- 16 - Revision A06
7.9.3 CAS Latency field (A6 to A4)
This field specifies the number of clock cycles from the assertion of the Read command to the first
data read. The minimum values of CAS Latency depend on the frequency of CLK.
A6 A5 A4 CAS LATENCY
0 0 0 Reserved
0 0 1 Reserved
0 1 0 2
0 1 1 3
1 0 0 Reserved
1 0 1 Reserved
1 1 0 2.5
1 1 1 Reserved
7.9.4 DLL Reset bit (A8)
This bit is used to reset DLL. When the A8 bit is “1”, DLL is reset.
7.9.5 Mode Register/Extended Mode register change bits (BS0, BS1)
These bits are used to select MRS/EMRS.
BS1 BS0 A11-A0
0 0 Regular MRS Cycle
0 1 Extended MRS Cycle
1 x Reserved
