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W9412G6CH

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型号: W9412G6CH
PDF文件:
  • W9412G6CH PDF文件
  • W9412G6CH PDF在线浏览
功能描述: 2M × 4 BANKS × 16 BITS DDR SDRAM
PDF文件大小: 1636.45 Kbytes
PDF页数: 共55页
制造商: WINBOND[Winbond]
制造商LOGO: WINBOND[Winbond] LOGO
制造商网址: http://www.winbond.com
捡单宝W9412G6CH
PDF页面索引
120%
W9412G6CH
Publication Release Date:Jul. 04, 2007
- 14 - Revision A06
7.9 Mode Register Operation
The mode register is programmed by the Mode Register Set command (MRS/EMRS) when all banks
are in the idle state. The data to be set in the Mode Register is transferred using the A0 to A11 and
BS0, BS1 address inputs.
The Mode Register designates the operation mode for the read or write cycle. The register is divided
into five filed: (1) Burst Length field to set the length of burst data (2) Addressing Mode selected bit to
designate the column access sequence in a Burst cycle (3) CAS Latency field to set the assess time in
clock cycle (4) DLL reset field to reset the DLL (5) Regular/Extended Mode Register filed to select a
type of MRS (Regular/Extended MRS). EMRS cycle can be implemented the extended function (DLL
enable/Disable mode)
The initial value of the Mode Register (including EMRS) after power up is undefined; therefore the
Mode Register Set command must be issued before power operation.
7.9.1 Burst Length field (A2 to A0)
This field specifies the data length for column access using the A2 to A0 pins and sets the Burst
Length to be 2, 4 and 8 words.
A2 A1 A0 BURST LENGTH
0 0 0 Reserved
0 0 1 2 words
0 1 0 4 words
0 1 1 8 words
1 x x Reserved
7.9.2 Addressing Mode Select (A3)
The Addressing Mode can be one of two modes; Interleave mode or Sequential Mode, When the
A3 bit is “0”, Sequential mode is selected. When the A3 bit is “1”, Interleave mode is selected. Both
addressing Mode support burst length 2, 4 and 8 words.
A3 ADDRESSING MODE
0 Sequential
1 Interleave
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