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W9412G6CH

W9412G6CH首页预览图
型号: W9412G6CH
PDF文件:
  • W9412G6CH PDF文件
  • W9412G6CH PDF在线浏览
功能描述: 2M × 4 BANKS × 16 BITS DDR SDRAM
PDF文件大小: 1636.45 Kbytes
PDF页数: 共55页
制造商: WINBOND[Winbond]
制造商LOGO: WINBOND[Winbond] LOGO
制造商网址: http://www.winbond.com
捡单宝W9412G6CH
PDF页面索引
120%
W9412G6CH
Publication Release Date: Jul. 04, 2007
- 13 - Revision A06
7.5 Precharge
There are two Commands, which perform the precharge operation (Bank Precharge and Precharge
All). When the Bank Precharge command is issued to the active bank, the bank is precharged and
then switched to the idle state. The Bank Precharge command can precharge one bank independently
of the other bank and hold the unprecharged bank in the active state. The maximum time each bank
can be held in the active state is specified as t
RAS (max). Therefore, each bank must be precharged
within t
RAS(max) from the bank activate command.
The Precharge All command can be used to precharge all banks simultaneously. Even if banks are
not in the active state, the Precharge All command can still be issued. In this case, the Precharge
operation is performed only for the active bank and the precharge bank is then switched to the idle
state.
7.6 Burst Termination
When the Precharge command is used for a bank in a Burst cycle, the Burst operation is terminated.
When Burst Read cycle is interrupted by the Precharge command, read operation is disabled after
clock cycle of (CAS Latency) from the Precharge command. When the Burst Write cycle is interrupted
by the Precharge command, the input circuit is reset at the same clock cycle at which the precharge
command is issued. In this case, the DM signal must be asserted “high” during t
WR to prevent writing
the invalided data to the cell array.
When the Burst Read Stop command is issued for the bank in a Burst Read cycle, the Burst Read
operation is terminated. The Burst read Stop command is not supported during a write burst operation.
Refer to the diagrams for Burst termination.
7.7 Refresh Operation
Two types of Refresh operation can be performed on the device: Auto Refresh and Self Refresh. By
repeating the Auto Refresh cycle, each bank in turn refreshed automatically. The Refresh operation
must be performed 4096 times (rows) within 64mS. The period between the Auto Refresh command
and the next command is specified by t
RFC.
Self Refresh mode enters issuing the Self Refresh command (CKE asserted “low”) while all banks are
in the idle state. The device is in Self Refresh mode for as long as CKE held “low”. In the case of
distributed Auto Refresh commands, distributed auto refresh commands must be issued every 15.6 µS
and the last distributed Auto Refresh commands must be performed within 15.6 µS before entering the
self refresh mode. After exiting from the Self Refresh mode, the refresh operation must be performed
within 15.6 µS. In Self Refresh mode, all input/output buffers are disabled, resulting in lower power
dissipation (except CKE buffer). Refer to the diagrams for Refresh operation.
7.8 Power Down Mode
Two types of Power Down Mode can be performed on the device: Active Standby Power Down Mode
and Precharge Standby Power Down Mode.
When the device enters the Power Down Mode, all input/output buffers are disabled resulting in low
power dissipation (except CKE buffer).
Power Down Mode enter asserting CKE “low” while the device is not running a burst cycle. Taking
CKE “high” can exit this mode. When CKE goes high, a No operation command must be input at next
CLK rising edge. Refer to the diagrams for Power Down Mode.
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