W83877TF/W83877TG
Publication Release Date: May 2006
-89- Revision 0.7
This register is used for the high speed modem application. While the bit is set to logic 1 it can make
the baudrate of UART up to 921.2KBPS (the clock source of UART is 14.769MHz) for high speed
transmit/receive.
Bit 7 - bit 2: Reserved.
FASTA (Bit 1):
0 the clock source of UART A is the same as the frequency of TURA (CR0C bit 7)
and SUAMIDI (CR3 bit 1) selected.
1 the clock source of UART A is 14.769MHZ.
FASTB (Bit 0):
0 the clock source of UART B is the same as the frequency of TURB (CR0C bit 6)
and SUBMIDI (CR3 bit 0) selected.
1 the clock source of UART B is 14.769MHZ.
11.2.26 Configuration Register 20 (CR20)
When the device is in Extended Function mode and EFIR is 20H, the CR20 register can be accessed
through EFDR. Default = FCH if CR16 bit 2 = 1; default = 00H if CR16 bit 2 = 0. The bit definitions
are as follows:
1
2
34567
0
reserved
reserved
FDCAD2
FDCAD3
FDCAD4
FDCAD5
FDCAD6
FDCAD7
This register is used to select the base address of the Floppy Disk Controller (FDC) from 100H-3F0H
on 16-byte boundaries. NCS = 0 and A10 = 0 are required to access the FDC registers. A[3:0] are
always decoded as 0xxxb.
FDCAD7-FDCAD2 (Bit 7-bit 2): match A[9:4]. Bit 7 = 0 and bit 6 = 0 disable this decode.
Bit 1-bit 0: Reserved, fixed at zero.
11.2.27 Configuration Register 23 (CR23)
When the device is in Extended Function mode and EFIR is 23H, the CR23 register can be accessed
through EFDR. Default = DEH if CR16 bit 2 = 1; default = 00H if CR16 bit 2 = 0. The bit definitions are
as follows:
