W83877TF/W83877TG
Publication Release Date: May 2006
-87- Revision 0.7
DSPRLGRQ (Bit 2):
0 enable PRT legacy mode on IRQ and DRQ selections. DCR bit 4 has effect on
selecting IRQ.
1 disable PRT legacy mode on IRQ and DRQ selections. DCR bit 4 has no effect on
selecting IRQ.
DSUALGRQ (Bit 1):
0 enable UART A legacy mode on IRQ selection. MCR bit 3 has effect on selecting IRQ.
1 disable UART A legacy mode on IRQ selection. MCR bit 3 has no effect on selecting
IRQ.
DSUBLGRQ (Bit 0):
0 enable UART B legacy mode on IRQ selection. MCR bit 3 has effect on selecting IRQ.
1 disable UART B legacy mode on IRQ selection. MCR bit 3 has no effect on selecting
IRQ.
11.2.24 Configuration Register 18 (CR18), default=00H
When the device is in Extended Function mode and EFIR is 18H, the CR18 register can be accessed
through EFDR. The bit definitions are as follows:
1
2
34567
0
SHARA
SHARB
SHARC
SHARD
SHARE
SHARF
SHARG
SHARH
This register is used to select whether these interrupt request pins are in the IRQ sharing mode. While
in the IRQ sharing mode, the corresponding pin is low active for 200ns for the interrupt request and
keeps tri-stated otherwise.
SHARH (Bit 7):
0 pin IRQ_H in the legacy ISA IRQ mode.
1 pin IRQ_H in the IRQ sharing mode.
SHARG (Bit 6):
0 pin IRQ_G in the legacy ISA IRQ mode.
1 pin IRQ_G in the IRQ sharing mode.
