W83877TF/W83877TG
Publication Release Date: May 2006
-85- Revision 0.7
GDA1IPI (Bit 0): See below.
GDA1OPI GDA1IPI
0 0
GIOP1 functions as a data pin, and GIOP1
→SD1, SD1→GIOP1
0 1
GIOP1 functions as a data pin, and inverse GIOP1
→SD1, SD1→
GIOP1
1 0
GIOP1 functions as a data pin, and GIOP1
→SD1, inverse SD1→
GIOP1
1 1
GIOP1 functions as a data pin, and inverse GIOP1
→ SD1, inverse
SD1
→GIOP1
11.2.22 Configuration Register 16 (CR16), default = 04H
When the device is in Extended Function mode and EFIR is 16H, the CR16 register can be accessed
through EFDR. The bit definitions are as follows:
1
2
34567
0
HEFRAS
reserved
PNPCVS
reserved
G0IQSEL
G1IQSEL
reserved
reserved
Bit 7-bit 6: Reserved.
G1IQSEL (Bit 5):
0 pin 96 function as IRQ_A.
1 pin 96 function as GIO1.
The corresponding power-on setting pin is NRTSB (pin 45).
G0IQSEL (Bit 4):
0 pins 92 function as IRQ_B.
1 pins 92 function as GIO0.
The corresponding power-on setting pin is NRTSB (pin 45).
Bit 3: Reserved.
PNPCVS (bit 2):
0 PnP-related registers (CR20, CR23-29) reset to be all 0s.
1 default settings for these registers.
