W83877TF/W83877TG
Publication Release Date: May 2006
-81- Revision 0.7
11.2.18 Configuration Register 12 (CR12), default = 00H
When the device is in Extended Function mode and EFIR is 12H, the CR12 register can be accessed
through EFDR. The bit definitions are as follows:
1
2
34567
0
GIO1AD7
GIO1AD0
GIO1AD1
GIO1AD2
GIO1AD3
GIO1AD4
GIO1AD5
GIO1AD6
GIO1AD7-GIO1AD0 (Bit 7-bit 0): GIOP1 (pin 96) address bit 7-bit 0.
11.2.19 Configuration Register 13 (CR13), default = 00H
When the device is in Extended Function mode and EFIR is 13H, the CR13 register can be accessed
through EFDR. The bit definitions are as follows:
1
2
34567
0
G1CADM1
GIO1AD8
GIO1AD9
GIO1AD10
reserved
G1CADM0
reserved
reserved
G1CADM1-G1CADM0 (bit 7, 6): GIOP1 address bit compare mode selection
G1CADM1 G1CADM0 GIOP1 PIN
0 0 compare GIO1AD10-GIO1AD0 with SA10-SA0
0 1 compare GIO1AD10-GIO1AD1 with SA10-SA1
1 0 compare GIO1AD10-GIO1AD2 with SA10-SA2
1 1 compare GIO1AD10-GIO1AD3 with SA10-SA3
Bit 5- bit 3: Reserved
GIO1AD10-GIO1AD8 (Bit 2-bit 0): GIOP1 (pin 96) address bit 10-bit 8.