W83877TF/W83877TG
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11.2.14 Configuration Register D (CR0D), default = A3H
When the device is in Extended Function mode and EFIR is 0DH, the CR0D register can be accessed
through EFDR. The bit definitions are as follows:
1
2
34567
0
SIRTX1
SIRTX0
SIRRX1
SIRRX0
HDUPLX
IRMODE2
IRMODE1
IRMODE0
SIRTX1 (Bit 7): IRTX pin selection bit 1
SIRTX0 (Bit 6): IRTX pin selection bit 0
SIRTX1 SIRTX0 IRTX OUTPUT ON PIN
0 0 disabled
0 1 IRTX1 (pin 43)
1 0 IRTX2 (pin 95)
1 1 disabled
SIRRX1 (Bit 5): IRRX pin selection bit 1
SIRRX0 (Bit 4): IRRX pin selection bit 0
SIRRX1 SIRRX0 IRRX INPUT ON PIN
0 0 disabled
0 1 IRRX1 (pin 42)
1 0 IRRX2 (pin 94)
1 1 disabled
HDUPLX (Bit 3):
0 The IR function is Full Duplex.
1 The IR function is Half Duplex.
IRMODE2 (Bit 2): IR function mode selection bit 2
IRMODE1 (Bit 1): IR function mode selection bit 1
IRMODE0 (Bit 0): IR function mode selection bit 0
