W83877TF/W83877TG
Publication Release Date: May 2006
-75- Revision 0.7
Table 11-4
BIT 5 OF TDR BIT 4 OF TDR
RWC
RWC
= 0
RWC
= 1
0 0 Normal 250K bps 500K bps
0 1 0 1.2 M FDD X
1 0 1 X 1.4M FDD
1 1 X X X
Bit 4: Reserved.
CHIP ID 3, CHIP ID 2, CHIP ID 1, CHIP ID 0 (Bit 3-bit 0):
These four bits are read-only bits that contain chip identification information. The value is 0CH for
W83877TF/TG during a read.
11.2.11 Configuration Register A (CR0A), default = 00H
When the device is in Extended Function mode and EFIR is 0AH, the CRA register can be accessed
through EFDR. This register is reserved.
11.2.12 Configuration Register B (CR0B), default = 0CH
When the device is in Extended Function mode and EFIR is 0BH, the CRB register can be accessed
through EFDR. The bit definitions are as follows:
1
2
34567
0
DRV2EN
INVERTZ
IDENT
ENIFCHG
MFM
RXW4C
TXW4C
reserved
Bit 7: Reserved.
TXW4C (Bit 6):
This bit is active high. When active, the IR controller will wait for a 4-character period of time after the
end of last receiving before it can start transmitting data.
RXW4C (Bit 5):
This bit is active high. When active, the IR controller will wait for a 4-character period of time after the
end of last transmitting before it can start receiving data.
ENIFCHG (Bit 4):
This bit is active high. When active, it enables host interface mode change, which is determined by
IDENT (Bit 3) and MFM (Bit 2).