W83877TF/W83877TG
Publication Release Date: May 2006
-67- Revision 0.7
00 Normal Mode (Default), PRTMOD2 = 0
Default state after power-on reset. In this mode, the W83877TF is fully compatible with
the SPP and BPP mode.
01 Extension FDD Mode (EXTFDD), PRTMOD2 = 0
10 Reserved, PRTMOD2 = 0
11 Extension 2FDD Mode (EXT2FDD), PRTMOD2 = 0
00 Reserved, PRTMOD2 = 1
01 EPP Mode and SPP Mode, PRTMOD2 = 1
10 ECP Mode, PRTMOD2 = 1
11 ECP Mode and EPP Mode, PRTMOD2 = 1
Bit 1: Reserved.
IPD (Bit 0):
This bit is used to select the W83877TF/TG's legacy power-down functions. When the bit 0 is set to 1,
W83877TF/TG will stop its clock internally and enter power-down (IPD) mode immediately.
W83877TF/TG will not leave the power-down mode until either a system power-on reset from the MR
pin or this bit is reset to 0 to program the chip back to power-on state.
11.2.2 Configuration Register 1 (CR1), default = 00H
When the device is in Extended Function mode and EFIR is 01H, the CR1 register can be accessed
through EFDR. The bit definitions are as follows:
7 6 5 4 3 2 1 0
reserved
reserved
reserved
reserved
reserved
reserved
reserved
ABCHG
ABCHG (Bit 7):
This bit enables the FDC AB Change Mode. Default to be enabled at power-on reset.
0 Drives A and B assigned as usual
1 Drive A and drive B assignments exchanged
Bit 6-bit 0: Reserved.
