W83877TF/W83877TG
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10. SERIAL IRQ
W83877TF/TG supports a serial IRQ scheme. This allow a signal line to be used to report the legacy
ISA interrupt requests. Because more than one device may need to share the signal serial IRQ signal
line, an open drain signal scheme is used. The clock source is the PCI clock. The serial interrupt is
transferred on the IRQSER signal, one cycle consisting of three frames types: a start frame, several
IRQ/Data frame, and one Stop frame. The serial interrupt scheme adheres to the
Serial IRQ
Specification for PCI System, Version 6.0.
Timing Diagrams For IRQSER Cycle
Start Frame timing with source sampled a low pulse on IRQ1
SL
or
H
HRTSRTS SRRTT
IRQ2 FRAMEIRQ1 FRAMEIRQ0 FRAMESTART FRAME
START
1
IRQ1
IRQ1 NoneNoneHost Controller
H=Host Control SL=Slave Control R=Recovery T=Turn-around S=Sample
PCICLK
IRQSER
Drive Source
1. Start Frame pulse can be 4-8 clocks wide.
Stop Frame Timing with Host using 17 IRQSER sampling period
TSR TSSRRT
NEXT CYCLESTOP FRAME
IRQ14
STOP
1
IRQ15 NoneNone Host Controller
H=Host Control I=IdleR=Recovery T=Turn-around S=Sample
PCICLK
IRQSER
Drive
1. Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode.
FRAME
IRQ15
FRAME
IOCHCK
FRAME
I
2
HRT
START
3
2. There may be none, one or more Idle states during the Stop Frame.
3. The next IRQSER c
cle's Start Frame pulse ma
or ma
not start immediatel
after the turn-around clock of the Stip Frame.
