W83877TF/W83877TG
Publication Release Date: May 2006
-57- Revision 0.7
Bit 2: Read/Write
1 Disables DMA and all of the service interrupts.
0 Enables one of the following cases of interrupts. When one of the service interrupts
has occurred, the serviceIntr bit is set to a 1 by hardware. This bit must be reset to
0 to re-enable the interrupts. Writing a 1 to this bit will not cause an interrupt.
(a) dmaEn = 1:
During DMA this bit is set to a 1 when terminal count is reached.
(b) dmaEn = 0 direction = 0:
This bit is set to 1 whenever there are writeIntr Threshold or more bytes free in the
FIFO.
(c) dmaEn = 0 direction = 1:
This bit is set to 1 whenever there are readIntr Threshold or more valid bytes to be
read from the FIFO.
Bit 1: Read only
0 The FIFO has at least 1 free byte.
1 The FIFO cannot accept another byte or the FIFO is completely full.
Bit 0: Read only
0 The FIFO contains at least 1 byte of data.
1 The FIFO is completely empty.
7.3.11 Bit Map of ECP Port Registers
D7 D6 D5 D4 D3 D2 D1 D0 NOTE
Data
PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
ecpAFifo
Addr/RLE Address or RLE field 2
Dsr
nBusy nAck PError Select nFault 1 1 1 1
Dcr
1 1 Directio ackIntEn SelectIn nInit autofd strobe 1
cFifo
Parallel Port Data FIFO 2
ecpDFifo
ECP Data FIFO 2
tFifo
Test FIFO 2
cnfgA
0 0 0 1 0 0 0 0
cnfgB
compress intrValue 1 1 1 1 1 1
Ecr
MODE nErrIntrEn dmaEn serviceIntr full empty
Notes:
1. These registers are available in all modes.
2. All FIFOs use one common 16-byte FIFO.
