W83877TF/W83877TG
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7.3.10 ecr (Extended Control Register) Mode = all
This register controls the extended ECP parallel port functions. The bit definitions are follows:
Empty
Full
Service Intr
DMA En
nErrIntr En
MODE
MODE
MODE
7 6 54 32 1 0
Bit 7-5: These bits are read/write and select the mode.
000 Standard Parallel Port mode. The FIFO is reset in this mode.
001 PS/2 Parallel Port mode. This is the same as 000 except that direction may be used
to tri-state the data lines and reading the data register returns the value on the data
lines and not the value in the data register.
010 Parallel Port FIFO mode. This is the same as 000 except that bytes are written or
DMAed to the FIFO. FIFO data are automatically transmitted using the standard
parallel port protocol. This mode is useful only when direction is 0.
011 ECP Parallel Port Mode. When the direction is 0 (forward direction), bytes placed
into the ecpDFifo and bytes written to the ecpAFifo are placed in a single FIFO and
transmitted automatically to the peripheral using ECP Protocol. When the direction
is 1 (reverse direction) bytes are moved from the ECP parallel port and packed into
bytes in the ecpDFifo.
100 Selects EPP Mode. In this mode, EPP is active if the EPP supported option is
selected.
101 Reserved.
110 Test Mode. The FIFO may be written and read in this mode, but the data will not be
transmitted on the parallel port.
111 Configuration Mode. The confgA and confgB registers are accessible at 0x400 and
0x401 in this mode.
Bit 4: Read/Write (Valid only in ECP Mode)
1 Disables the interrupt generated on the asserting edge of nFault.
0 Enables an interrupt pulse on the high to low edge of nFault. If nFault is asserted
(interrupt) an interrupt will be generated and this bit is written from a 1 to 0.
Bit 3: Read/Write
1 Enables DMA.
0 Disables DMA unconditionally.
