W83877TF/W83877TG
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5.2.9 Configuration Control Register (CC Register) (Write base address + 7)
This register is used to control the data rate. In the PC/AT and PS/2 mode, the bit definitions are as
follows:
xxxx xx
DRATE0
DRATE1
0
1
2
3
4
5
7
6
X:
Reserved
Bit 7-2: Reserved. These bits should be set to 0.
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC.
In the PS/2 Model 30 mode, the bit definitions are as follows:
1
2
34567
0
DRATE0
DRATE1
NOPREC
XX
XX X
X
: Reserved
Bit 7-3: Reserved. These bits should be set to 0.
NOPREC (Bit 2):
This bit indicates no precompensation. It has no function and can be set by software.
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC.
