W83877TF/W83877TG
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5.2 Register Descriptions
There are several status, data, and control registers in W83877TF/TG. These registers are defined
below:
ADDRESS REGISTER
OFFSET READ WRITE
base address + 0
base address + 1
base address + 2
base address + 3
SA REGISTER
SB REGISTER
TD REGISTER
DO REGISTER
TD REGISTER
base address + 4 MS REGISTER DR REGISTER
base address + 5 DT (FIFO) REGISTER DT (FIFO) REGISTER
base address + 7 DI REGISTER CC REGISTER
5.2.1 Status Register A (SA Register) (Read base address + 0)
This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2
mode, the bit definitions for this register are as follows:
1
2
34567
0
WP
INDEX
HEAD
TRAK0
STEP
DRV2
INIT PENDING
DIR
INIT PENDING (Bit 7):
This bit indicates the value of the floppy disk interrupt output.
DRV2 (Bit 6):
0 A second drive has been installed
1 A second drive has not been installed
STEP (Bit 5):
This bit indicates the complement of
STEP output.
TRAK0 (Bit 4):
This bit indicates the value of
TRAK0 input.
HEAD (Bit 3):
This bit indicates the complement of
HEAD output.
0 side 0
1 side 1
