W83877TF/W83877TG
Publication Release Date: May 2006
-119- Revision 0.7
These bits indicate the status of the SCI input, which is set when the device's IRQ is raised. If the
corresponding enable bit in the SCI interrupt enable register (in GP0EN1) is set, an SCI interrupt is
raised and routed to the output pin. Writing a 1 clears the bit, and writing a 0 has no effect. If the bit is
not cleared, new IRQ for the SCI logic input is ignored, therefore no SCI interrupt is raised.
BIT NAME DESCRIPTION
0 URBSCISTS UART B SCI status, which is set by the UART B IRQ.
1 URASCISTS UART A SCI status, which is set by the UART A IRQ.
2 FDCSCISTS FDC SCI status, which is set by the FDC IRQ.
3 PRTSCISTS PRT SCI status, which is set by the printer port IRQ.
4-7 Reserved Reserved.
11.4.14 General Purpose Event 0 Status Register 2 (GP0STS2)
Register Location: <CR34>+1H System I/O Space
Default Value: 00h
Attribute: Read/write
Size: 8 bits
1
2
34567
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
BIT NAME DESCRIPTION
0-7 Reserved Reserved. These bits always return a value of zero.
11.4.15 General Purpose Event 0 Enable Register 1 (GP0EN1)
Register Location: <CR34> +2H System I/O Space
Default Value: 00h
Attribute: Read/write
Size: 8 bits