W83877TF/W83877TG
-118 -
BIT NAME DESCRIPTION
0-7 TMR_VAL This read-only field returns the running count of the power management
timer. This is a 24-bit counter that runs off of a 3.579545 MHZ clock, and
counts while in the system working state. The timer is reset and then
continues counting until the CLKIN input the the chip is stopped. If the clock
is restarted without a MR reset, then the counter will continue counting from
where it stopped. The TMR_STS bit is set any time the last bit of the timer
(bit 23) goes from 0 to 1 or from 1 to 0. If the TMR_EN bit is set, the setting
of the TMR_STS bit will generate an SCI interrupt.
11.4.12 Power Management 1 Timer 4 (PM1TMR4)
Register Location: <CR33>+BH System I/O Space
Default Value: 00h
Attribute: Read only
Size: 8 bits
1
2
34567
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
BIT NAME DESCRIPTION
0-7 Reserved Reserved. These bits always return a value of zero.
11.4.13 General Purpose Event 0 Status Register 1 (GP0STS1)
Register Location: <CR34> System I/O Space
Default Value: 00h
Attribute: Read/write
Size: 8 bits
1
2
34567
0
URBSCISTS
URASCISTS
FDCSCISTS
PRTSCISTS
Reserved
Reserved
Reserved
Reserved