W83877TF/W83877TG
Publication Release Date: May 2006
-117- Revision 0.7
11.4.10 Power Management 1 Timer 2 (PM1TMR2)
Register Location: <CR33>+9H System I/O Space
Default Value: 00h
Attribute: Read only
Size: 8 bits
1
2
34567
0
TMR_VAL8
TMR_VAL9
TMR_VAL10
TMR_VAL11
TMR_VAL12
TMR_VAL13
TMR_VAL14
TMR_VAL15
BIT NAME DESCRIPTION
0-7 TMR_VAL This read-only field returns the running count of the power management
timer. This is a 24-bit counter that runs off of a 3.579545 MHZ clock, and
counts while in the system working state. The timer is reset and then
continues counting until the CLKIN input the the chip is stopped. If the clock
is restarted without a MR reset, then the counter will continue counting from
where it stopped. The TMR_STS bit is set any time the last bit of the timer
(bit 23) goes from 0 to 1 or from 1 to 0. If the TMR_EN bit is set, the setting
of the TMR_STS bit will generate an SCI interrupt.
11.4.11 Power Management 1 Timer 3 (PM1TMR3)
Register Location: <CR33>+AH System I/O Space
Default Value: 00h
Attribute: Read only
Size: 8 bits
1
2
34567
0
TMR_VAL16
TMR_VAL17
TMR_VAL18
TMR_VAL19
TMR_VAL20
TMR_VAL21
TMR_VAL22
TMR_VAL23