W83877TF/W83877TG
Publication Release Date: May 2006
-5- Revision 0.7
4. PIN DESCRIPTION
(Note: Refer to section 12.2 DC CHARACTERISTICS for details.)
I/O8tc - TTL level output pin with 8 mA source-sink capability; CMOS level input voltage
I/O12t - TTL level bi-directional pin with 12 mA source-sink capability
I/O24t - TTL level bi-directional pin with 24 mA source-sink capability
OUT8t - TTL level output pin with 8 mA source-sink capability
OUT12t - TTL level output pin with 12 mA source-sink capability
OD12 - Open-drain output pin with 12 mA sink capability
OD24 - Open-drain output pin with 24 mA sink capability
INt - TTL level input pin
INts - TTL level Schmitt-triggered input pin
INc - CMOS level input pin
INcs - CMOS level Schmitt-triggered input pin
4.1 Host Interface
SYMBOL PIN I/O FUNCTION
D0−D7
66-73 I/O
24t
System data bus bits 0-7.
A0−A9
51-55
57-61
IN
t
System address bus bits 0-9.
A10 75 IN
t
In ECP Mode, this pin is the A10 address input.
IOCHRDY 5 OD
24
In EPP Mode, this pin is the IO Channel Ready output to extend
the host read/write cycle.
MR 6 IN
ts
Master Reset. Active high. MR is low during normal operations.
CS
2 IN
t
Active low chip select signal.
AEN 62 IN
t
System address bus enable.
IOR
63 IN
ts
CPU I/O read signal.
IOW
64 IN
ts
CPU I/O write signal.
DRQ_B 100 OUT
12t
DMA request signal B.
DACK_B
98 IN
ts
DMA Acknowledge signal B.
DRQ_C 4 OUT12t DMA request signal C.
DACK_C
18 INts DMA Acknowledge signal C.
TC 97 INts Terminal Count. When active, this pin indicates termination of a
DMA transfer.
IRQIN 93 INt Interrupt request input for IRQ routing ; For example , the IRQ12
can be routed into this port when PS/2 mouse is not installed.