W83877TF/W83877TG
-112 -
11.4.1 Power Management 1 Status Register 1 (PM1STS1)
Register Location: <CR33> System I/O Space
Default Value: 00h
Attribute: Read/write
Size: 8 bits
1
2
34567
0
TMR_STS
Reserved
Reserved
Reserved
BM_STS
GBL_STS
Reserved
Reserved
BIT NAME DESCRIPTION
0 TMR_STS This bit is the timer carry status bit. This bit gets set anytime the bit 23 of the
24-bit counter changes(whenever the MSB changes from low to high or high
to low). While TMR_EN and TMR_STS are set a power magnet event is
raised. This bit is only set by hardware and can only be cleared by the
software writing a 1 to this bit position. Writing a 0 has no effect.
1-3 Reserved Reserved.
4 BM_STS This is the bus master status bit. Writing a 1 to BM_CNTRL also sets
BM_STS. Writing a 1 clears this bit and also clears BM_CNTRL. Writing a 0
has no effect.
5 GBL_STS This is the global status bit. This bit is set when the BIOS want the attention
of the SCI handler. BIOS sets this bit by setting BIOS_RLS and can only be
cleared by software writing a 1 to this bit position. Writing a 1 to this bit
position also clears BIOS_RLS. Writing a 0 has no effect.
6-7 Reserved Reserved. These bits always return a value of zero.
11.4.2 Power Management 1 Status Register 2 (PM1STS2)
Register Location: <CR33>+1H System I/O Space
Default Value: 00h
Attribute: Read/write
Size: 8 bits
1
2
34567
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
WAK_STS
