W83877TF/W83877TG
Publication Release Date: May 2006
-101- Revision 0.7
URBCNT7 - URBCNT0 (Bit 7 - bit 0): UART B idle timer count.
This register is used to specify the initial value of UART B idle timer. Once UART B enters the working
state (that is, after any access to this device, any IRQ, and any external input), the power down
machine of UART B reloads this count value and the idle timer counts down. When the timer counts
down to zero, UART B enters the power down state ,i.e., sleeping state. If this register is set to 00H,
the power down function will be invalid. The time resolution of this value is minute or second, which is
defined by the TMIN_SEL bit of CR3A. Note that (1). this register is valid only when the power
management function of UART B is enabled, that is, CHIPPME=1 (CR32 bit 7) and URBPME=1
(CR32 bit 0), (2). If the register is set to 00H, UART B will remain in the current state(working or
sleeping).
11.2.42 Configuration Register 37 (CR37), default=00H
When the device is in Extended Function mode and EFIR is 37H, the CR37 register can be accessed
through EFDR. The bit definitions are as follows:
1
2
34567
0
FDCCNT0
FDCCNT1
FDCCNT2
FDCCNT3
FDCCNT4
FDCCNT5
FDCCNT6
FDCCNT7
FDCCNT7 - FDCCNT0 (Bit 7 - bit 0): FDC idle timer count.
This register is used to specify the initial value of FDC idle timer. Once FDC enters the working state
(that is, after any access to this device, any IRQ, and any external input), the power down machine of
FDC reloads this count value and the idle timer counts down. When the timer counts down to zero,
FDC enters the power down state ,i.e., sleeping state. If this register is set to 00H, the power down
function will be invalid. The time resolution of this value is minute or second, which is defined by the
TMIN_SEL bit of the CR3A. Note that (1). this register is valid only when the power management
function of FDC is enabled, that is, CHIPPME=1 (CR32 bit 7) and FDCPME=1 (CR32 bit 2), (2). If the
register is set to 00H, FDC will remain in the current state(working or sleeping).
11.2.43 Configuration Register 38 (CR38), default=00H
When the device is in Extended Function mode and EFIR is 38H, the CR38 register can be accessed
through EFDR. The bit definitions are as follows:
1
2
34567
0
PRTCNT0
PRTCNT1
PRTCNT2
PRTCNT3
PRTCNT4
PRTCNT5
PRTCNT6
PRTCNT7
