W83877TF/W83877TG
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11.2.33 Configuration Register 29 (CR29)
When the device is in Extended Function mode and EFIR is 29, the CR29 register can be accessed
through EFDR. Default = 62H if CR6 bit 2 = 1; default = 00H if CR16 bit 2 = 0. The bit definitions are
as follows:
1
2
34567
0
IQNIQS0
IQNIQS1
IQNIQS2
IQNIQS3
FDCIQS0
FDCIQS1
FDCIQS2
FDCIQS3
FDCIQS3-FDCIQS0 (Bit 7-bit 4): Allocate interrupt resource for FDC.
IQNIQS3-IQNIQS0 (Bit 3-bit 0): Allocate interrupt resource for IRQIN.
11.2.34 Configuration Register 2C (CR2C), default=00H
When the device is in Extended Function mode and EFIR is 2CH, the CR2C register can be accessed
through EFDR. The bit definitions are as follows:
1
2
34567
0
reserved
reserved
CLKINSEL
reserved
reserved
reserved
reserved
reserved
Bit 7 - bit 3 : Reserved.
CLKINSEL (Bit 2): Clock input frequency selection.
This pin should be reset/set according the CLKIN pin.
0 the clock source on CLKIN pin is 24 MHz.(default)
1 the clock source on CLKIN pin is 48 MHz.
Bit 1- bit 0: Reserved.